1. Field of the Invention
The present invention relates to a metal pattern and a method of forming the same, and more particularly to a metal contact pattern and a method of forming the metal contact pattern for use in a semiconductor apparatus, such as a mask programmable read only memory, a photoelectrical conversion apparatus or a signal processing apparatus, a semiconductor apparatus which includes an electrostatic capacity device, a semiconductor integrated circuit including an LDD transistor and a Schottky-diode or an image reading or recording semiconductor device.
2. Related Background Art
The conventional technology has experienced the following problems at the time of forming a pattern on an electrode or the like of the foregoing devices.
(1) Selective Formation of Contact of Mask ROM
A mask ROM is a semiconductor memory for exclusively use to write data with a mask for photolithography for use in a process for manufacturing a semiconductor. The mask ROM is widely used to serve as a fixed memory of a computer, a data memory of a kanji generator or a voice synthesizer or program software of a TV game. FIG. 1 is a circuit diagram of the mask ROM having MOS transistors which are disposed to form a matrix and on which data is written. Since a variety of methods of writing data on the mask ROM are available, corresponding manufacturing methods are employed. Data is written by a method in which the threshold voltage of the gate is varied or a method in which data is written depending upon whether or not the contact is present on the drain region of the transistor. The threshold voltage of the gate is varied by a method in which the thickness of an oxide film of the gate is changed, a method in which channel dope ions are selectively injected after the gate oxide film has been formed, a method in which channel dope ions are further selectively injected through a polysilicon electrode with high energy after the polysilicon gate electrode has been formed or a method in which channel dope ions are selectively injected through an aluminum circuit or a passivation film with large energy of 1 MeV or larger after the aluminum circuit or the passivation film has been formed. The foregoing methods will now be described. The method in which the thickness of the gate oxide film is changed and a method in which the channel dope ions are selectively injected by a photolithographic mask after the gate oxide film has been formed are omitted from description because they encounter a problem that a too long manufacturing process must be performed after data has been written.
FIGS. 2A to 2C illustrate the process for manufacturing the mask ROM by the conventional method, in which the injection of the channel dope ions is performed selectively through the polysilicon electrode with high energy after the polysilicon gate electrode has been performed to write data. FIG. 2A illustrates the cross section of MOS transistors formed by a known technology. Field oxide films 2 are formed on a P-type Si substrate 1, and the MOS transistor devices are separated from each other. Gate electrodes 4 made of polysilicon are formed on gate oxide films 3, and channel regions 5 are formed under the gate oxide films 3. Further, source regions 6 and drain regions 7 are formed so that an inter-layer insulating film 8 in the form of a non-dope silicate glass (NSG)/BPSG structure is formed by CVD. It should be noted that proper channel doping is performed in the channel regions 5 by ion injection. That is, the state where the MOS transistor is turned off is maintained even if voltage corresponding to negative logic "0" is applied to the gate. If voltage corresponding to positive logic "1" is applied to it, the MOS transistor is turned on. FIG. 2B illustrates a manufacturing process corresponding to writing of data. After a photo-resist 20 has been applied, a mask on which data is written is used to pattern the photo-resist 20. Then, B-ions 21 are injected under conditions that energy is about 200 KeV to about 400 KeV and the amount of dose is about 1.times.5.times.10.sup.13 cm.sup.-2 if the minimum size is determined by a 1.2 .mu.m rule although the foregoing conditions are varied depending upon the degree of integration of the mask ROM. The thickness of the photo-resist is determined depending upon the energy. After channel dope ions for writing data have been injected, the photo-resist 20 is removed to reflow the inter-layer insulating film. The reason why the reflow is performed is that the inter-layer insulating film must be flattened and the channel-doped ions B must be electrically activated. A MOS transistor positioned in the right portion of FIG. 2B has the channel region 5 in which ions B are doped so that the threshold voltage is sufficiently higher than the voltage corresponding to the positive logic "1". Therefore, even if the voltage corresponding to the positive logic "1" is applied to the gate, the state where the right MOS transistor is turned off is maintained. FIG. 2C illustrates the final cross sectional structure. Contact holes 9 are formed in the source region 6, the gate oxide film 3 on the drain region 7 and the inter-layer insulating film 8, and aluminum lines 18 are formed so that a passivation film 19 made of SiN is formed.
FIGS. 3A and 3B illustrate a process for manufacturing a mask ROM by the conventional method. The foregoing method is a method in which aluminum lines or a passivation film is formed, and then the channel dope ion injection is selectively performed through the aluminum lines or the passivation film with large energy of 1 MeV or larger so that data is written. FIG. 3A illustrates the cross section of a state where MOS transistors are formed by the known method. A field oxide film 2 is formed on the P-type Si substrate 1 and the MOS transistor devices are separated from one another. Channel regions 5 are formed under gate oxide films 3. Further, source regions 6 and drain regions 7 are formed so that an inter-layer insulating films 8 in the form of the (NSG)/BPSG structure are formed by CVD. Contact holes 9 are formed through the source regions 6, the gate oxide films 3 on the drain regions 7 and the inter-layer insulating films 8 so that aluminum lines 18 are formed. Further, a passivation film 20 made of SiN is formed. In this example, the aluminum lines 18 are not present on the gate electrodes 4. Proper channel doping is performed in the channel regions 5 by ion injection. That is, even if voltage corresponding to negative logic "0" is applied to the gate, the state where the MOS transistor is turned off is maintained. However, if voltage corresponding to positive logic "1" is applied to the gate, the MOS transistor is turned on.
FIG. 3B illustrates a manufacturing process corresponding to writing of data. After a photo-resist 20 has been applied, a mask on which data is written is used to pattern the photo-resist 20. Then, B-ions 21 are injected under conditions which vary depending upon whether or not the aluminum line 18 is present on the gate electrode 4 of the mask ROM or whether or not the channel dope ion injection for writing data is performed through the passivation film 19. Energy of 1 MeV or larger is needed, and the amount of the dose is about 1 to 10.times.10.sup.13 cm.sup.-2. After channel dope ions for writing data have been injected, the photo-resist 20 is removed. Then, heat treatment is performed in order to electrically activate channel-doped ions B. Since the aluminum lines 15 have been formed, the heat treatment is performed at 450.degree. C. or lower. The right MOS transistor shown in FIG. 3B has the channel region 5 in which ions B are doped so that the threshold voltage is sufficiently higher than the voltage corresponding to the positive logic "1". Therefore, even if the voltage corresponding to the positive logic "1" is applied to the gate, the state where the right MOS transistor is turned off is maintained. The foregoing second conventional example has no ensuing process.
FIGS. 4A to 4B illustrate a third conventional example of the process for manufacturing the mask ROMs, wherein data is written depending upon whether or not a contact is present on a drain region. FIG. 4A illustrates the cross section of a state where MOS transistors are formed by the known technology. A field oxide film 2 is formed on a P-type Si substrate, and the MOS transistor devices are separated from one another. Gate electrodes 4 made of polysilicon are formed on gate oxide films 3. Further, channel regions 5 are formed under the gate oxide films 3. In addition, source regions 6 and drain regions 7 are formed so that an inter-layer insulating film 8 in the form of an NSG/BPSG structure is formed by CVD. Proper channel doping is performed in the channel regions 5 by ion injection. That is, even if voltage corresponding to negative logic "0" is applied to the gate, the state where the MOS transistor is turned off is maintained. If voltage corresponding to positive logic "1" is applied to the gate, the MOS transistor is turned on.
FIGS. 4B and 4C illustrate a manufacturing process which corresponds to writing of data. After a photo-resist 20 has been applied, a mask, on which data has been written, is used to pattern the photo-resist 20. Then, contact holes 9 are formed in the source regions 6, the gate oxide film 3 on the drain regions 7 and the inter-layer insulating film 8 before aluminum lines 18 are formed. The right MOS transistor shown in FIG. 4C has no contact hole in the gate insulating film 3 on the drain region 6 and the inter-layer insulating film 8. Therefore, the right MOS transistor is not applied with power supply voltage VDD. Therefore, even if voltage corresponding to positive logic "1" is applied to the gate, the state where the MOS transistor is turned off is maintained. FIG. 4D illustrates a final cross section. Thus, a passivation film 19 made of SiN is formed.
Since data is written on the mask ROM in the manufacturing process, it has considerable custom characteristics. Therefore, the mask ROM must be delivered in a short period (TAT: time around time) from a moment of receipt of data from a customer to a moment of delivery as well as meeting requirements, such as high degree of integration, low electric power consumption and low cost and the like, generally required for a memory. If the data writing process is performed in the first half of the manufacturing process, an error of written data or that occurring in the mask manufacturing process causes the delivery data to be further delayed.
Although the first conventional example exhibits a relatively short TAT because data is written after the gate electrode has been formed, the TAT is longer than that realized by the second or the third conventional example. Even worse is, the fact that data writing can be performed by injecting ions with large energy of 200 to 400 KeV prevents use of a general ion injecting apparatus. Therefore, an exclusive large-energy ion injecting apparatus must be used and, accordingly, the cost to manufacture the mask ROM cannot be reduced.
Since the second conventional example is arranged to write data after the passivation film has been formed, it exhibits a considerably short TAT which takes one or two days in addition to days taken to manufacture the mask. However, the heat treatment can be performed only under a low temperature of 450.degree. C. or lower after the aluminum lines have been performed. Therefore, defects generated due to the injection of channel dope ions for writing data cannot be recovered completely. Further, only about 50% of channel-doped ions B can be electrically activated. If ions are injected with large energy in MeV levels, there arises a problem in that defects cannot completely be restored even if the heat treatment is performed at high temperature. Therefore, a problem of reliability arises. Further, if the aluminum line is present on the gate electrode, the channel dope ion injection causes aluminum atoms to be introduced into the gate channel region due to the knock-on phenomenon. What is worse, the cost to manufacture the mask ROM cannot be reduced as compared with the first conventional example because the price of the MeV-level high energy ion injecting apparatus is high and its manufacturing performance is unsatisfactory.
The third conventional example does not need a special manufacturing apparatus raising the cost to manufacture the mask ROM and exhibits a short TAT as compared with the first conventional example. However, the necessity that the contact region is formed for each memory cell raises a technical problem in that the chip area cannot be reduced.
With any one of the foregoing methods, many days are required to manufacture the mask on which data will be written. It leads to a fact that the mask must be manufactured again if there is a data error. Therefore, even if the TAT is short after the mask has been manufactured, the overall TAT cannot be shortened satisfactorily.
(2) Semiconductor Integrated Circuit Having Capacitor
Conventional Example AI
Some semiconductor integrated circuits include a multiplicity of electrostatic capacity devices. With the recent rise in the density of the integrated circuits and high speed operation, there has been a desire for reducing the size of the capacitor device and enlarging the capacity.
FIG. 5 is a schematic cross sectional view which illustrates a general MOS capacitor for use in the conventional integrated circuit. FIG. 7 illustrates its equivalent circuit.
The MOS capacitor is arranged in such a manner that an n.sup.+ layer 1103 formed on an n.sup.- layer 1102 embedded in a p-type substrate 1101 is made to be a lower electrode layer. Further, a pullout electrode 1106 from an upper electrode 1105 and the n.sup.+ layer 1103 are formed while interposing a dielectric layer 1104. A terminal A and a terminal B of the equivalent circuit respectively correspond to the upper electrode 1105 and the lower pullout electrode 1106.
As shown in FIG. 6 in which the equivalent circuit is illustrated, a conductor, such as an n.sup.+ diffusion layer is used to form the lower electrode 1103, the MOS capacitor has parasitic devices, such as a diode D and a capacitor Ccs. Further, it includes a resistance component R.sub.1 made of the n.sup.+ diffusion layer and disposed between the capacitor C.sub.1 and the terminal B. As the upper electrode 1105, Al or polysilicon is used generally. If polysilicon is used, a resistance component R.sub.2 is added between the terminal A and the capacitor C.sub.1.
Therefore, if a MOS capacitor is used, it includes parasitic devices such as the resistor, the capacitor and the diode in addition to the capacitor C.sub.1. As a result, the influences of the parasitic devices limits the frequency characteristics of the MOS capacitor.
If either of the terminals of the capacitor device is used under a high impedance, capacity division occurs between C.sub.1 and Ccs due to the presence of the parasitic device Ccs.
Further, the capacity can be undesirably changed due to the CV characteristics of the MOS structure depending upon the polarity of the applied voltage.
FIG. 7 is a schematic cross sectional view which illustrates a pn junction capacitor which is generally used in an integrated circuit. FIG. 9 illustrates its equivalent circuit. The foregoing capacitor is arranged such that an n.sup.- layer 1102, a p-layer 1107 and n.sup.+ layers 1103 and 1108 are formed on a p-type substrate 1101 while causing electrodes 1109 and 1110 to face each other while interposing a dielectric layer 1104.
The structure shown in FIG. 7 and terminals of the equivalent circuit shown in FIG. 8 are made to correspond to one another with symbols shown in FIGS. 7 and 8. Although the capacity between terminals X and Y is C.sub.2 +C.sub.3, any pn junction may be used as the capacitor.
Since the pn junction capacitor includes the parasitic resistor and the parasitic capacitor, the frequency characteristics are limited due to their influences. Furthermore, its capacity considerably depends upon the voltage. Further, it cannot be used in a case where the pn junction is invert bias.
FIG. 9 is a schematic cross sectional view which illustrates a capacitor device formed into metal-insulating film-metal structure developed to overcome the foregoing problems experienced with the MOS capacitor or the pn junction capacitor.
The foregoing capacitor device comprises a lower metal layer (a lower electrode) 1202 and an inter-layer insulating film 1203 each of which is formed on a semiconductor substrate 1201, an upper metal layer (an upper electrode) 1204 and a thin insulating film (dielectric layer) 1205 serving as a capacitor portion.
As the metal layers for forming the upper and lower layers, any one of the following material has been used: Al, Al alloy or tungsten manufactured by, for example, a magnetron sputtering method or tungsten manufactured by, for example, a chemical vapor-phase deposition method (a CVD method). As the thin insulating layer 1205 serving as the capacitor, SiO.sub.2, Si.sub.3 N.sub.4 or Ta.sub.2 O.sub.5 prepared by the CVD method or Al.sub.2 O.sub.3 prepared by an anode oxidation method or their mixture has been employed.
The foregoing capacitor device exhibits an advantage that the parasitic capacitance and the parasitic resistance are not generated.
As an electrostatic capacitor device for use in a dynamic RAM or the like, a circuit has been known in which a capacitor is connected to the drain of a MOSFET as shown in FIG. 10. FIG. 11 illustrates a device structure, called a "stack-type structure" capable of realizing a circuit of the foregoing type. The foregoing structure is arranged such that a polysilicon layer 1030 is formed to be in contact with a drain 1025 of a pMOSFET which comprises a polysilicon gate 1023 on a gate oxide film 1022 formed on a p-type substrate 1021, a source 1024, a drain 1025, a source electrode 1026, a field oxide film 1027, an oxide film 1028 and an inter-layer insulating film 1029. Further, a polysilicon layer 1032 is formed while interposing a dielectric film 1031 so that the capacitor is formed. A trench-type capacitor shown in FIG. 12 and a fin-type capacitor shown in FIG. 13 are arranged to respectively have polysilicon layers 1030A and 1032A and 1030B and 1032B formed into modified shapes in order to enlarge the capacitance of the stack type capacitor and to reduce the size of the same.
The circuit of a storage device (hereinafter called a "memory cell") of the semiconductor circuit has been structured, for example, as shown in FIG. 14. The schematic cross section of a memory cell of the foregoing types is shown in FIG. 15. As shown in FIG. 15, a capacitor C serving as a capacitor device included in the memory cell comprises a lower electrode 1030, an upper electrode 1032 and a dielectric film 1031 formed between the foregoing two electrodes 1030 and 1032.
If the foregoing memory cell must be formed at a high degree of integration, the plane area of the capacitor C serving as the capacitor portion for each bit must be reduced. In order to operate the memory cell normally, resistance against a soft error occurring due to .alpha.-rays radiated from a ceramic package of, for example, a DRAM must be maintained by storing a charge amount of about 200 fC. Assuming that the power supply voltage determined to be 5 V depending upon the foregoing charge amount and that the capacity between the source and the earth of the capacitor C is expressed by Cs, the following relationship is held: EQU Cs.gtoreq.40 fF
If the dielectric film 1031 is made of an ordinary Si oxide film, it is known that electric field E, which can be applied to the dielectric film 1031, is about E&lt;5 MV/cm in terms of maintaining reliability of the Si oxide film. Therefore, it has been considered that the thickness of the Si oxide film, which can be used satisfactorily as the dielectric film, is 50 .ANG. if a method applying voltage which is the half of the power supply voltage is applied. Since dielectric constant .DELTA.r of the Si oxide film is 3.7, the capacitor C must have a plane area of 6 .mu.m.sup.2 in order to realize Cs.gtoreq.40 fF. A memory cell having the capacity, the plane area of which is large, cannot meet the foregoing recent requirement of raising the degree of integration. Accordingly, the surface area of a capacitor formed into a stacked structure has been increased by forming its shape into a downward projection or an upward projection while preventing the enlargement of the projective plane area of the capacitor C, so that a required capacity has been maintained.
As can be understood from the description about conventional example AI, the memory cell must enlarge the capacity of the capacitor thereof and reduce the area of the device as well as satisfy the desire for the improvement in the electrostatic capacitor device.
However, the foregoing stack-type memory cell cannot simultaneously realize the enlargement of the capacitor and the reduction of the device area. The trench-type memory cell encounters a problem of leakage occurring in the capacitor thereof. The fin-type memory cell has a problem that the manufacturing process is too complicated due to the complex shape of the polysilicon. Therefore, there arises a problem in that a memory cell, in which a satisfactory degree of integration is realized and the cost of which can be reduced, cannot easily be provided.
That is, the conventional technology cannot easily form a large capacity capacitor requiring only a small area at satisfactory manufacturing yield due to its structure and the manufacturing method to be improved.
Conventional Example BI
Hitherto, the side wall (a spacer) of an LDD transistor has been formed by a method comprising steps of forming an oxide film on the entire surface of silicon wafer by a CVD method and performing an anisotropic dry etching (etch back).
Since the foregoing conventional example BI has been arranged so that the formed oxide film is subjected to the anisotropic dry etching in order to form the side wall (the spacer), there arises the following problems:
(1) An etching back process must be performed. PA1 (2) It is difficult in the etch back process to control the shape of the side wall (the spacer). PA1 (3) The final point cannot easily be detected in the etch back process. PA1 (4) The device can be damaged due to ion impact occurring in the etch back process. PA1 (5) The distribution of the CVD oxide film within the wafer cannot easily be controlled.
Conventional Example CI
The performance of electronic devices and integrated circuits has been improved and the degree of integration of the same has been raised by fining their structures. As for the machining size, a marketed 4-Mbit DRAM comprising a MOSFET having a gate length of 0.8 .mu.m has been reported and an experimental product having a gate length 0.07 .mu.m has been reported. It has been considered that if the machining size is 0.1 .mu.m or smaller coherence of electronic waves and a tunnel phenomenon occurs considerably, causing an electronic device based on a novel physical phenomenon to be realized.
In order to further fine the conventional electronic device and the integrated circuit or to realize an electronic device based on a novel physical phenomenon, a stable precise machining technology in levels of 0.2 .mu.m or small must be established.
The conventional precise machining technology uses an organic resist film and performs etching by making use of the organic resist film as the etching mask. The foregoing method will now be described schematically with reference to FIGS. 16A to 16D and problems rising at the time of fining the structure will be described.
An assumption is made that a thin film 1402 is formed on a substrate 1401 as shown in FIG. 16A. The substrate 1401 is a Si substrate or Si wafer on which a SiO.sub.2 film has been formed. The thin film 1402 is made of metal, such as Al (aluminum) or an insulating film, such as BPSG or PSG. The thickness of the thin film 1402 ranges about 0.1 .mu.m to about 2 .mu.m. An organic resist 1403 is applied to the upper surface of the substrates 1401 and the thin film 1402. The material of the organic resist 1403 is made of well known AZ1350, PFPR, TSMR or PMMA. The thickens of the organic resist 1403 ranges about 0.1 .mu.m to about 2 .mu.m.
Then, the substrate comprising the organic resist 1403, the thin film 1402 and the substrate 1401 as shown in FIG. 16A is irradiated with energy beams 1405, such as ultraviolet rays or electron beams, as shown in FIG. 16B. In this irradiation operation, the resist which has been selectively exposed, that is, the resist pattern 1404, is irradiated with the ultraviolet rays or the electron beams in its portion having a width of L.sub.1. The organic resist in the region L.sub.1 irradiated with light or the electronic beams is sensitized before it is immersed in a developer. As a result, the organic resist in only the portion irradiated with light is removed as shown in FIG. 16C. As a result, a developed resist, that is, the resist pattern 1406 is formed if the resist is a positive-type resist. If the resist is a negative-type resist, the organic resist in the portion irradiated with the light or the electron beams is left after the development has been completed.
Then, an etching process shown in FIG. 16D is performed in such a manner that an organic resist 1408 serves as a mask to etch the thin film in the opened portion of the organic resist 1408 so that the thin film is patterned as designated by 1407.
In the foregoing conventional example C, even if the width of the portion which is, as shown in FIGS. 16A to 16D, irradiated with the ultraviolet rays or the electron beams 1405, is L.sub.1 as shown in FIG. 16B, it slightly changes to L.sub.2 as shown in FIG. 16C at the time of the development and to L.sub.3 as shown in FIG. 16D at the time of the etching process. Therefore, it has been very difficult to make the machining width L.sub.3 shown in FIG. 16D to 0.2 .mu.m or less.
That is, the thin film is etched and the organic resist 1408 is etched as well in the etching process, L.sub.3 is different from L.sub.2 undesirably.
If the thin film 1402 is made of metal, such as Al (aluminum), another problem of disconnections of lines takes place due to irregular reflection of light. It leads to a fact that the width of the line cannot easily be controlled. As a result, the size of the lines cannot be reduced at the time of designing the device and, accordingly, a problem arises at the time of performing the precise machining.
(3) Semiconductor Device Including Short Diode
(Conventional Example AII)
Hitherto, a Schottky TTL having a clamping structure which uses a diode having no storage effect and which is disposed between the collector and the base has been used.
FIGS. 17A and 17B respectively are a typical cross sectional view and an equivalent circuit diagram of a Schottky TTL. Referring to FIGS. 17A and 17B, reference numeral 2201 represents a silicon substrate, 2202 represents a collector of a bipolar transistor, 2203 represents a base of the bipolar transistor, 2204 represents an emitter of the bipolar transistor, 2205 represents an aluminum layer constituting the Schottky diode, 2206 represents an aluminum line for connecting the emitter 2204, and 2207 represents an aluminum line for connecting the collector 2202.
If the device having the foregoing structure is intended to be integrated densely, the emitter diffusion layer 2204 must be joined up in a shallow portion. Further, the contact hole in the emitter line 2206 and the collector line 2207 must be formed precisely.
However, if the depth of the diffusion in the emitter 2204 is shallower than 0.2 .mu.m, spikes of the aluminum line arises a risk of a short circuit occurring between the base and the emitter.
If the depth of the contact hole in the emitter line 2206 or the collector line 2207 is 1 .mu.m or shallower, the contact resistance increases in the n-type diffusion layer particularly.
In order to overcome the foregoing problems, it is preferable that a barrier metal layer made of TiN or TiW is placed in the lower layer of the metal line of the emitter line 2206 and the collector line 2207.
However, the portion 2205 of foregoing conventional Example A in which the Schottky diode is structured encounters a problem that the Schottky characteristics cannot be attained between the aluminum and the silicon if the barrier metal is present in the surface in which the metal and the silicon are joined up.
That is, it is preferable that the emitter contact 2206 and the collector contact 2207 have the barrier metal stacked to serve as a contact metal layer with the semiconductor layer. On the other hand, it is preferable that the base and the Schottky diode contact 2205 are formed into structures in which aluminum is stacked in the lowermost portion of the metal layer.
However, use of the foregoing conventional manufacturing method raises the following problem of complication.
That is, the contact hole of the emitter and the collector is first formed, and then the barrier metal is deposited by sputtering or the like. Then, aluminum is deposited, the emitter and the collector lines are patterned to have predetermined forms, and then an insulating film is deposited. Then, the contact hole is again formed in the base and the shot key diode portion, aluminum is deposited, and then the base electrode is patterned to have a predetermined shape.
As described above, the conventional method encounters a problem that the number of the manufacturing processes cannot be decreased similarly to the two-layer metal lines.
Conventional Example BII
Hitherto, a contact sensor for use in a facsimile machine or the like using single crystal silicon has been so formed that a plurality of chips are disposed on a line and the chips are joined up to have a predetermined length for the contact sensor. If an A4 paper sheet is read, 11 chips must be joined up in order to read the A4 paper sheet in a case where each chip has a length of 2 cm.
An apparatus, such as a printer, for recording an image sometimes has a printer head formed into a monolisic structure and mounted on a silicon single crystal base thereof. The foregoing case is exemplified by a foaming-type ink jet head disclosed in Japanese Patent Application Laid-Open No. 57-72867.
Also in this case, a plurality of chips must be arranged or mechanical head drive must be performed because the dimension of the chip has been about 2 cm.
Further, conventional example B encounters the following problems:
(1) Since a plurality of chips are joined up, the deviation of the chip configuration generates a step in the image. Therefore, the image resolution is restricted depending upon the accuracy in the chip configuration. PA0 (2) The image recording head, which must be mechanically driven, involves the performing of unnecessary reciprocating motion encounters a problem of unsatisfactory printing speed in addition to the problem of the step occurring in the joined portion.
An optimum method of overcoming the foregoing two problems is to form the head by a long and single chip which is capable of collectively reading or collectively printing, for example, an A4 paper sheet.
If the reading or printing head portion is constituted by a single chip adapted to A4 size, the single chip must have a length longer than 21 cm.
It means a that the size must be larger than 9 inches if an ordinary circular silicon substrate is used. If an effective region in which a chip can be formed in a circular substrate is intended to be 60% or more, the circular substrate must have a diameter of 15 inches or more.
Therefore, the size of the apparatus must have an excessively large size and the manufacturing cost is enlarged. Therefore, although superior performance can be attained in comparison to the conventional structure, it is difficult to put the foregoing technology into practical use.
(4) Formation of Metal Pattern While Aligning to Alignment Mark
With the recent rise of the degree of integration of the semiconductor apparatus, the contact size is fined to approach the resolution limit of quarter micron level from the half micron level. On the other hand, the trend of thinning the thickness of the inter-layer insulating film is restricted because the line capacity must be maintained at a small quantity. Therefore, fining of the longitudinal direction of the contact has not been made satisfactorily. As a result, the aspect ratio is raised with the trend of fining of the contact size.
The conventional method of forming the metal film mainly composed of Al and based on the sputtering method encounters a problem of disconnection of the contact portion due to the fall of the step coverage.
Hitherto, the method of forming the metal film by sputtering has been replaced by a known method in which the contact hole is filled with metal by CVD and a metal film for forming a circuit is formed by sputtering or CVD to flatten the surface of the metal film. In this case, an alignment mark for aligning the mask for forming the circuit pattern is, as shown in FIGS. 18A and 18B, arranged such that a step is formed prior to forming the metal for constituting the circuit and a step formed on the surface of the metal circuit is utilized as the alignment mark. The difference in the intensity of reflected light between the projection portion and the pit portion is utilized to confirm the position of the wafer.
Referring to FIGS. 18A and 18B, reference numeral 3001 represents a semiconductor base, 3002 represents a field insulating film, 3004 represents an inter-layer insulating film, 3005 represents a metal film to serve as a circuit, 3003 represents an insulating film thinner than the field insulating film 3002, and 3006 represents a step serving as the alignment mark.
The alignment at the time of patterning the metal circuit must be performed by minimizing the position deviation between the contact hole and the metal circuit pattern. Therefore, the step of the contact hole is utilized to form the alignment mark and the metal pattern for forming the circuit is aligned to the alignment mark so that the position deviation is minimized.
However, the step of the contact hole substantially disappears in the process in which the contact hole is filled with the metal by the CVD method. Therefore, the alignment mark for the metal circuit pattern must be formed prior to forming the contact hole. Therefore, the area of the alignment margin including the contact hole step serving as the alignment mark is larger by 20 to 30% in the process having the step of filling the contact hole. The first aspect of the present invention is able to overcome the foregoing technical problem.
On the other hand, the conventional CVD technology has the following problems to be dissolved. A first problem is that the metal cannot be filled at a high aspect ratio by the sputtering method and, accordingly, the desire of fining the lines and forming a multi-layer structure cannot be met. A second problem is that the selective enlargement based on the thermal CVD method cannot realize reliable selectiveness and, accordingly, the Al film is enlarged in an undesirable portion on the oxide film. A third problem is that a necessity for a portion, in which the film is not intended to be enlarged, to be completely covered with the oxide film usually increases the processes for oxidation, separation of the oxide film and patterning the resist. Therefore, the manufacturing process cannot be arranged freely.